Managing power and power related issues in application specific integrated circuits (ASICs) and standard silicon products (SSPs) is becoming increasingly difficult. One area of particular concern is dynamic power and instantaneous current draw in 1 Volt technologies. A current/power spike typically occurs around the switching of a clock or clocks in a design. The design has to provide for the current to switch the circuits. One way the designer can account for the current is with an energy/current density function curve.
Referring to FIG. 1, a diagram 10 is shown illustrating example energy/current density function curves 12 and 14. In an ideal case, all of the current would be evenly distributed during a clock cycle as illustrated by the curve 12. An evenly distributed current demand allows the design to use a simple robust power grid without decoupling capacitors (DCAPs). However, because most switching occurs around the clock transitions, most of the time the current demand distribution is far from ideal, as illustrated by the curve 14. Instead, a design has to accommodate a power spike at the beginning of the clock cycle. If the spike is not eliminated, problems can occur. Some examples of problems include: (i) the power grid can ring at some harmonic related to the clock; (ii) the voltage can dip below a storage element retention level; (iii) the timing can fail due to low voltage performance loss. Higher speed designs that tend to be zero skew in nature can make the problems even worse.
Conventional solutions include compensation and avoidance. A conventional compensation technique involves using special circuit elements that act as local power reserves to supply enough current to allow switching with minimum power supply noise and droop. The special circuit elements can include some form of capacitor. A common version is a decoupling capacitor (DCAP). Another compensation technique involves using a very robust power grid. A conventional avoidance technique uses intentional manipulation of the clocks within the design in an attempt to distribute the current demand. If the clocks can be skewed in a controlled fashion, the current demand can be redistributed and the spike reduced.
The conventional solutions have significant problems. The problems become increasingly worse as the frequency of the design increases and when datapath logic is involved. Decoupling capacitors (DCAPs) are becoming more and more expensive to use. As the industry moves to progressively finer technology nodes, the DCAPs are becoming less capacitive, more resistive, and/or less area optimized. At the same time, leakage currents associated with the DCAPs are progressively increasing.
The compensation and avoidance techniques can be used together to help manage issues surrounding dynamic power. In order to compensate for the current spike associated with the dynamic power, the leakage power is increased. In addition, since the amount of capacitance provided by the DCAPs is decreasing, the amount of area consumed by the DCAPs must be increased to compensate. In a design using conventional techniques, the DCAP area can be larger than the logic area. For slower speed logic a 35% area increase is routinely seen. Both of the above problems, substantial area and leakage increases, represent significant issues that can become progressively worse as circuit geometries shrink and frequencies increase.
Creating a very robust power grid can help somewhat, but is not usually sufficient by itself. However, as the power grid is enhanced, the amount of routing resources are decreased or metal layers have to be added. Both decreased routing resources and additional metal layers can represent significant problems. Moving clocks is possible, but involves progressively increasing complexity, progressive design closure uncertainty and diminishing returns as clock frequencies increase. There are a number of reasons why moving clocks can be complex. One reason is that the conventional practice is for a leaf node clock cell to drive many flip-flops. Changing a single clock buffer can affect many timing arcs. The affected timing arcs must still pass timing post optimization.
Because affected timing arcs must still pass timing post optimization, the number of valid targets can be limited or can make the timing results worse. When the number of valid targets is limited or the timing results worsen, the design can become un-closable. In addition, as clock frequencies increase, the opportunities to effectively exploit the technique of moving clocks decreases because the relationship between the total clock cycle and the amount of delay associated with the intentional clock tree skew for power degrades.